1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the invention relates to an operating method for a semiconductor memory device having reduced test initialization time.
This application claims the benefit of Korean Patent Application No. 10-2006-0064624, filed Jul. 10, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Contemporary semiconductor memory devices are generally characterized by increased integration density and decreased power consumption. In order to achieve these results, the constituent transistors must have longer effective channel lengths, but reduced overall physical size. These properties have been obtained in the recess channel array transistor (RCAT) and a sphere shaped recess channel array transistor (SRCAT). As a result, these types of transistors are now commonly used memory cell transistors in semiconductor memory devices.
However, when a semiconductor memory device is realized using these types of cell transistors, the device routinely fails an initial power test. Indeed, this initial testing failure at the chip level is all but expected given the unique operating properties of these device types. Fortunately, subsequently applied testing, particularly module level testing, yields useful test results. Thus, the initial test failure may be ignored or bypassed.
In conventionally applied test methods, this initial test failure phenomenon may be effectively “skipped” in several fashions. For example, a dummy CAS before RAS (CBR) refresh operation and a dummy write operation may be used to exercise the memory cell transistors one or more times. Thereafter, an actual test operation may be performed. In effect, the preliminary exercise of the cell transistors prepares them for subsequent testing.
FIG. 1 is a block diagram illustrating an exemplary configuration for a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device comprises a memory cell array 10, a row decoder circuit 12, a column decoder circuit 14, a command decoder 20, a mode register setting circuit 22, a refresh address generating circuit 30, a CBR period control circuit 32, a bank selecting circuit 40, an address latch 42, a data output circuit 50, a data input circuit 52, and a power supply circuit 60.
The memory cell array 10 comprises a plurality of memory cell array banks 10-1 to 10-n, where “n” is the natural number. Each bank comprises a plurality of memory cells MC connected between a word line WL and a bit line BL. Each bank writes/reads data to/from a memory cell MC selected in response to one signal transmitted via word line WL and another signal transmitted via the bit line BL.
The row decoder circuit 12 comprises a plurality of row decoders 12-1 to 12-n which respectively correspond to a plurality of banks 10-1 to 10-n. The row decoder circuit 12 selects one bank and at least one word line for a memory operation in accordance with a bank selecting signal BS and a row address RAi. Alternately, the row decoder circuit 12 selects all banks simultaneously and at least one word line in each bank in accordance with a bank selecting signal BC and a refresh address RRAi. The row decoder circuit 12 also terminates the operation indicated by the bank selecting signal BC and the refresh address RRAi in response to a CBR end signal CBRE.
The column decoder circuit 14 comprises a plurality of column decoders 14-1 to 14-n which respectively correspond to a plurality of banks 10-1 to 10-n. The column decoder circuit 14 selects one bank and at least bit line BL to perform a read or write operation in accordance with a column address CAi. The column decoder circuit 14 also terminates the operation indicated by the column address CAi in response to the CBR end signal CBRE.
The command decoder 20 receives and combines externally applied command signals COM to generate, for example, an active signal ACT, a write signal WR, a read signal RD, a CBR signal CBR, and a mode register signal MRS. Collectively, these control signals determine an operating state for the semiconductor memory device. In particular, when a signal /CAS is applied before a signal /RAS, the command decoder 20 generates the CBR signal CBR for requesting a CBR refresh operation and supplies it to the refresh address generating circuit 30 and the CBR period control circuit 32.
The mode register setting circuit 22 receives and analyzes addresses Ai to determine whether a test mode is indicated when the mode register signal MRS is applied from the command decoder 20. The mode register setting circuit 22 generates a test signal TEST during a test mode.
The refresh address generating circuit 30 performs an up or down counting operation whenever the CBR refresh operation is requested, (i.e., whenever the CBR signal is applied). The refresh address generating circuit 30 generates the refresh addresses RRAi for sequentially selecting the word lines according to the count result and supplies it to the row decoder 12. That is, whenever the CBR refresh operation is requested, the refresh addresses RRAi for sequentially selecting the word lines are generated.
The CBR period control circuit 32 calculates lapsed time when the CBR signal is applied from the command decoder 20, and generates the CBR end signal CBRE following a particular time lapse of tREF. The CBR end signal CBRE is supplied to the row decoder 12 and the column decoder 14 so that the next CBR refresh operation can be performed. Here, the lapsed time tREF is defined as the time until the next CBR refresh operation is performed after the CBR refresh operation is performed. As well known in the art, this time period defines the CBR refresh operation time.
The bank selecting circuit 40 decodes a plurality of externally applied bank addresses BAj in order to generate a bank selecting signal BS selecting one of a plurality of banks 10-1 to 10-n. The bank selecting circuit 40 also generates the bank selecting signal BS for simultaneously selecting all of a plurality of banks 10-1 to 10-n when the CBR refresh operation is requested and so the CBR signal CBR is applied.
The address latch 42 determines a method for analyzing a plurality of externally applied addresses Ai in response to the active signal ACT, the write signal WR, and the read signal RD. The address latch 42 then latches a plurality of addresses Ai to be transmitted to the row decoder circuit 12 as the row address RAi during an activation command in which the active signal ACT is generated, and also latches a plurality of addresses Ai to be transmitted to the column decoder circuit 14 as the column address CAi during a read/write command in which the read/write signal WR/RD is enabled.
The data input circuit 52 receives data DIN from a data I/O pin (not shown) and supplies data din to the memory array 10 when a write operation is requested (i.e., when the write signal WR is applied).
The data output circuit 50 receives data dout output from the memory array 10 and supplies data DOUT to the data I/O pin (not shown) when the read operation is requested (i.e., when the read signal RD is applied).
The power supply circuit 60 receives an externally applied voltage EVC and generates an internal voltage IVC, a reference voltage VREF, a boosting voltage VPP, and a back bias voltage VBB as well as other operating and control voltages with the illustrated semiconductor memory device.
A test initialization method for a conventional semiconductor memory device, such as the one illustrated in FIG. 1, will now be explained with reference to the general flowchart of FIG. 2.
Test initialization begins with provision of a command COM and the addresses BAj and Ai to the semiconductor memory device. In response, the semiconductor memory device sequentially performs a power-up operation (S1), the dummy CBR refresh operation, the test mode setting operation, and the dummy write operation.
Thus, the semiconductor memory device is powered up (S1) and then performs the dummy CBR refresh operation at the tester's request. That is, the command COM for requesting the CBR refresh operation is repeatedly received within a predetermined time period, a plurality of row decoders 12-1 to 12-n sequentially select the word lines under control of the bank selecting circuit 40 and the refresh address generating circuit 30, and the refresh operation for the selected word line is performed (S2).
Subsequently, the semiconductor memory device sets the test mode through the mode register setting circuit 22 at the tester's request (S3) and then performs the dummy write operation. That is, a plurality of row decoders 12-1 to 12-n select one bank and one bit line under control of the bank selecting circuit 40 and the address latch 42, and a plurality of column decoders 14-1 to 14-n select one bit line to write data to one memory cell under control the address latch 42. The write operation is repeatedly performed until all memory cells in all banks write data (S4).
When the semiconductor memory device finishes the dummy CBR refresh operation and the dummy write operation, it confirms that the test initialization is complete and begins actual test operations under the control of the tester (S5). Any number of conventional test operations may now be performed.
As described above, the conventional semiconductor memory device separately performs the dummy CBR refresh operation and the dummy write operation during the test initialization to drive the cell transistor at least one time before beginning the actual test operation. While this approach accounts for the expected initial test failure, its also increases the time required to test time the semiconductor device, since the dummy CBR refresh operation and the dummy write operation must be performed for every test initialization. This is particularly true for the dummy write operation where only a single memory cell connected between one word line and one bit line may be selected and driven.